1. Field of the Invention
The present invention relates to a method of forming a metal line in a semiconductor device and, more particularly, to a method of forming a metal line in a semiconductor device capable of preventing reduction of contact areas due to parasitic spacers between metal plugs and metal lines, thereby improving contact resistance between them.
2. Discussion of Related Art
In a semiconductor device or electronic device, a metal line formation technology has been established and widely used. The metal line formation technology includes deposition of a conductive layer including materials such as aluminum (Al) and tungsten (W) on an insulating layer and patterning of the conductive layer by a typical photolithography process and a dry etching process. Particularly, with respect to the logic device requiring high integration and high performance among semiconductor devices, researches and developments in recent years have been focused on a method, which uses copper (Cu) instead of Al or W in order to reduce RC delay. In the aforementioned “RC”, the “R” means resistance of a line, and the “C” means dielectric constant of an insulating film.
In the metal line formation process using Cu, patterning becomes more difficult than in the process using Al or W. For this reason, trenches are formed first and then metal lines are formed to bury the trenches. This is called a damascene process. The process widely used at the present time includes a single damascene process and a dual damascene process. According to the single Damascene process, via holes are formed and buried with a conductive material, line trenches are formed on top of it, and then the trenches are buried with a line material again to form metal line. According to the dual Damascene process, via holes and line trenches are formed, and then the via holes and the line trenches are simultaneously buried with a line material to form metal line. Besides, a variety of methods have been proposed.
Meanwhile, it has been known that copper is very rapidly diffused through interstitial sites in silicon so that characteristics such as leakage current, threshold voltage, and saturation current can be deteriorated. For this reason, a copper layer cannot be used for a plug for making contact with a silicon substrate in a metal contact process. Therefore, a planarization process is performed by using a chemical mechanical polishing (CMP) method after contact holes for a metal contact are buried with tungsten plugs. As described above, if tungsten plugs are used to form a metal contact, parasitic spacers (in the circle shown in FIG. 7) occur between tungsten plugs and copper lines. This results in reducing contact areas, increasing resistance of lines, and decreasing reliability of lines. Furthermore, considering effects of line-end-shorting in the line trenches and an overlay margin of an exposure apparatus of 30 nm or more, it is easy to detect them by using technologies of 0.13 μm or less.